HAL CORTEX Overview ¶
Introducing CORTEX ¶
- group CORTEX_Introduction
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The CORTEX hardware abstraction layer provides a comprehensive set of APIs to interface with the Cortex core peripherals on STM32 microcontrollers. It enhances system control, interrupt management, and fault handling by offering flexible and efficient configuration of key core system blocks tailored to the ARMv8-M architecture.
It simplifies the configuration, initialization, and management of the Cortex core components, including the Nested Vector Interrupt Controller (NVIC), System Timer (SYSTICK), Memory Protection Unit (MPU), and System Control Block (SCB). Features supported include interrupt priority grouping, fault exception control, timer configuration, memory region protection, interrupt handling, and system information retrieval.
This abstraction layer guarantees portability and ease of use across different STM32 series.
Module and files ¶
The following diagram illustrates the CORTEX module and its associated files.
Component diagram ¶
The following diagram illustrates the software components involved in the CORTEX module. It shows the interactions between the user application, HAL drivers, low-level drivers, and the hardware components.
Configuration table ¶
The following table lists the configuration defines for the HAL CORTEX module, specifying their locations, default values, and descriptions:
- group CORTEX_Configuration_Table
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¶
Configuration inside the CORTEX driver ¶
Config defines
Description
Default value
Note
PRODUCT
from IDE
NA
The selected product.
USE_ASSERT_DBG_PARAM
from IDE
None
Allows to use the assert check parameters.
USE_HAL_CHECK_PARAM
from hal_conf.h
0
Allows to use the run-time checks parameters.
USE_HAL_CORTEX_MODULE
from hal_conf.h
1
Allows to use HAL CORTEX module.